View HI-8429_8959225.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HI-8429 8-channel gnd/open or supply/open sensor with programmable thresholds and spi interface general description features the HI-8429 is an 8-channel discrete-to-digital sensor fabricated with silicon-on-insulator (soi) technology designed to interface with a serial peripheral interface (spi). each input is individually configurable as either gnd/open or supply/open (28v/open). discrete input thresholds are programmable in the range of 2v to 12v. an spi bus is used to configure the sensors and to read sensor data . the part operates from a 3.3v ( 5%) digital supply and 12v to 15v analog supply. a 1ma wetting current is sourced from the input network on each sense input when gnd/open mode is selected for that pin. the wetting current serves to prevent dry relay or switch contacts. an optional debounce circuit also ensures sensor outputs respond correctly to mechanical sensor inputs. a sensor output interrupt pin alerts the system to a change in sensor input, avoiding constant polling via spi to check status. all sense inputs are internally lightning protected to rtca/do160g, section 22 level 3 pin injection test waveform set a(3 & 4), set b (3 & 5a) and set z (3 & 5b) without the using external components. higher levels of lightning protection can be achieved with an external series resistor and transorb at each sense input, refer to an305 for more details. spi programmable sensor thresholds sensor data read through spi bus robust cmos silicon-on-insulator (soi) technology eight discrete inputs, individually configurable as gnd/open or supply/open interrupt generated on any change of sensor state airbus abd0100h specification compliant mil-std-704 compliant sense inputs lightning protected to rtca/do1060g, section 22 level 3 10mhz serial peripheral interface (spi) allows daisy- chaining of parts for efficient board routing withstands inadvertent application of 115v ac/400hz power to sense inputs. internal self-test mode checks analog comparators february 2015 20-pin plastic small outline wide-body package pin configuration application avionics discrete to digital sensing holt integrated circuits (ds8429 rev. b) 02/15 www.holtic.com HI-8429psx 1 2 3 4 5 6 sense6 7 sense7 8 sense8 9 10 dnbc sense1 sense2 sense3 sense4 sense5 int 20 sel1 19 vdd 18 gnd 17 vlogic 16 sel0 15 si 14 13 sck 12 so 11 cs mr
block diagram HI-8429 holt integrated circuits 2 spi control vlogic gnd sel1 cs sck vdd figure 1. si vdd + - + - crn sense1-8 cr9 (test) vthi lightning protection v dd 20k 680k 10k 2k data register shift register mux test cr1 (psen1) cr2 (psen2) cr3 (psen3) cr4 (psen4) cr5 (psen5) cr6 (psen6) cr7 (psen7) cr8 (psen8) vtlo so por sense control sw1 sw2 config register sensor 1 sensor 2 sensor 3 sensor 4 sensor 5 sensor 6 sensor 7 sensor 8 sel0 dac register data8 data1 data2 data3 data4 data5 data6 data7 4 x 6 bit dac thresholds 4 x 6 bit dacs debounce interrupt generator dnbc mr int 4 x input matching networks
holt integrated circuits 3 HI-8429 pin pin symbol function description (soic) (qfn) 1 36 dnbc debounce enable i 2 2 sense1 33 44 55 66 88 10 15 11 16 12 17 13 22 14 23 15 24 16 25 discrete input 7 7 sense6 914 logic input nput; high = enabled. low = disabled, 10k pull-down to gnd sense input 1. mapped to last (eighth) spi bit shifted out of so during data read sense2 discrete input sense input 2. mapped to seventh spi bit shifted out of so during data read sense3 discrete input sense input 3. mapped to sixth spi bit shifted out of so during data read sense4 discrete input sense input 4. mapped to fifth spi bit shifted out of so during data read sense5 discrete input sense input 5. mapped to fourth spi bit shifted out of so during data read discrete input sense input 6. mapped to third spi bit shifted out of so during data read sense7 discrete input sense input 7. mapped to second spi bit shifted out of so during data read sense8 discrete input sense input 8. mapped to first spi bit shifted out of so during data read digital output interrupt output, generates a 1us low pulse when any sensor changes state, open drain logic input master reset, active low, internal 10k pull-up to vlogic so digital output spi data out sck logic input spi clock input. 10mhz maximum clock frequency. logic input chip select. spi data transfers are enabled when is low si logic input spi data input. sel0 logic input with sel1 selects spi function, see table 1 17 27 vlogic supply logic supply voltage 18 29 gnd supply ground 19 34 vdd supply analog supply voltage 20 35 sel1 logic input with sel0 selects spi function, see table 1, 10k pull-down to gnd int mr cs cs pin descriptions
functional description holt integrated circuits 4 configuration register data is loaded serially from the spi as described in the serial interface section below. the first bit of the configuration register (cr9) enables built-in-self test when set to a logic 1. for normal sensing operation, cr9 should be zero. the next eight configuration register bits (cr8-1) set the sensing mode for each sensor. if set to a high, the sensor is gnd/open, and if programmed to a low, the sensor is supply/open. data is shifted into the configuration register from the serial interface with bit cr9 first. writing a high in control register bit 9 puts the HI-8429 into the built-in test (bit) mode. in this mode setting a crn bit high for a particular sensor forces that comparator input high. a zero in crn forces the comparator input low. to verify correct operation, the user must read from the data register and compare this with the value written to cr1-8. HI-8429 overview the HI-8429 is comprised of 8 sensors, which may be individually configured for gnd/open or supply/open (also known as 28v/open) sensing. eight bits of the on-chip configuration register are used to set the sensor configuration. a high in the configuration register selects gnd/open and a low selects supply/open mode. a ninth bit in the configuration register is used to enable the chips built-in-test (bit) feature. the logical output from each sensor is latched into an eight-bit data register on the falling edge of the input. four internal 6 bit dacs provide the high and low thresholds. reading and writing to the registers is accomplished using a serial interface compatible with the industry-standard serial peripheral interface (spi) bus. figure 1 shows a simplified block diagram of the HI-8429. cs an open drain interrupt pin ( ) generates a 1 s low pulse when any of the sensor outputs change state. this frees up the micro-contoller from polling the register at frequent intervals. switches sw1 and sw2 (see figure 1) are open. the por also resets all the registers to the all zeros default state. pin can also be used to reset the device. a low on this pin has the same effect as por detailed above. during normal operation the pin should be left open or held high, if left open an internal 10k pulls the input up to vlogic. int mr mr reset and initialization the HI-8429 includes an on-chip power-on reset (por) circuit, which forces the sense inputs to a high-impedance state at power-up. the inputs remain high-impedance until the configuration register is programmed, defining the gnd/open (sw1 closed / sw2 open), or supply/open (sw1 open / sw2 closed) for each sensor. the HI-8429 registers are designed to retain programmed logic states through vlogic power dips down to 1.5v ensuring reliable operation in noisy environments without the need to re-initialize the part. an external 7654321 first bit shifted in from si cr3 cr2 cr4 cr5 8 cr6 cr7 cr8 bit enable cr1 9 last bit shifted in from si data register 7654321 first bit shifted out of so data3 data2 data4 data5 8 data6 data7 data8 data1 last bit shifted out of so the eight-bit data register captures the output state from the eight discrete sensors. data is latched on the falling edge of . the data bits are read out from the chip over the serial interface. sensor 8 data bit is output first at so followed by the remaining seven sensor states. in either mode (gnd/open or supply/open), a logic one is output when the voltage at the sensor pin input is greater than the high threshold and a logic zero is output when the sensor voltage is lower than the low threshold. multiple HI-8429s may be daisy-chained together to allow a single spi sequence to program configuration or capture data from several ics in one operation. cs supply/open sensing wetting current when programmed as supply/open sensors, crn is set to a logic 0. referring to figure 1, a switch in series with a diode is closed to provide a pull down to ground of 30k . as with gnd/open, supply/open sensor levels are set by dac thresholds vlo and vhi. for the supply/open case the wetting current into the sense input is simply the current sunk by the effective 30k to gnd. for v = 28v, i is 1ma. see figure 2. sense wet configuration register
holt integrated circuits 5 HI-8429 i (ma) sense v (v) sense -10 0 102030405060 1.75 1.55 1.35 1.15 0.95 0.75 0.55 0.35 0.15 -0.05 figure 2. supply/open mode sense input iv characteristic (vdd = 15v) i(a) sense v (v) sense -10 0 102030405060 60 50 40 30 20 10 0 -10 -20 figure 4. hi-z sense input iv characteristic (vdd = 15v) gnd/open sensing wetting current for gnd/open sensing, the crn bit is set to 1. referring to the block diagram, figure 1, this selection will connect a 12k pull-up resistance through a diode to vdd. this resistance gives extra noise immunity for detecting the open state while providing contact wetting current. open and closed states are detected according to the threshold levels glo and ghi programmed into the dac threshold register, see figures 14 - 17 for thresholds. when the sense input exceeds ghi, the output of the sensor goes high. the output of the sensor remains high until a voltage of less than glo is detected at the sense input, representing a valid ground state and causing the sensor output to go low. the sensor will maintain a ground detect state until the sense input becomes greater than ghi. the difference ghi - glo represents the hysteresis which improves noise immunity and reduces output chattering. in gnd/open mode a current is sourced from the sense pin when it is grounded and vdd is powered, see figure 3. this current called the wetting current serves to provide current through switches or relay contacts to prevent dry contacts and improve switch contact reliability. debounce when the input dbnc is high, a debounce circuit on the sensor outputs is enabled (see figure 1). the comparator outputs are sampled every 60ms, the state of the sensor register bit is changed only when two consecutive samples are identical. when debounce is enabled there will be approximately 60ms delay before the sense data register is updated. the 24-bits [t24:1] in the dac register program the sensor threshold levels for the eight discrete sensors. there are four 6 bit dacs: gl5:0 gnd/open low threshold gh5:0 gnd/open high threshold vl5:0 supply/open low threshold vh5:0 supply/open high threshold the thresholds are programmed according to the two formula below, for gnd/open and supply/open modes respecitvely: vthresh(g/o) = vdd x (0.126 + d/91.6) volts vthresh(s/o) = vdd x (0.144 + d/98.9) volts d is a value (0 to 63) programmed into the dac for further details see example dac threshold programming on page 11. dac threshold register i(a) sense v (v) sense -10 0 102030405060 figure 5. power-off sense input iv characteristics 350 300 250 200 150 100 50 0 -50 v =v =gnd dd logic v =v =open dd logic i (ma) sense v (v) sense -10 0 102030405060 0.2 -0.3 -0.8 -1.3 -1.8 -2.3 figure 3. gnd/open mode sense input iv characteristic (vdd = 15v)
configuration register spi transfers on power up or after a hardware reset all the sense input circuits are disabled by default, they only become enabled after a write to the configuration register. sel0 and sel1 are held low for sensor configuration changes, see table 1. write / read timing is identical to data register transfers, except with the added complication that the configuration register is nine bits rather than eight bits. care should be taken to ensure correct bit alignment when shifting data into and out of the register, particularly when daisy-chaining multiple devices. figures 6 - 10 show examples of spi data transfers, including a daisy- chained transfer. holt integrated circuits 6 functional description (cont.) dac threshold register t7 t6 t5 t4 t3 t2 t1 vh2 vh1 vh3 vh4 t8 vh0 last bit shifted out of so t11 t10 t9 t12 vh5 vl0 vl1 vl2 vl3 vl4 vl5 t19 t18 t17 t16 t15 t14 t13 first bit shifted out of so gh2 gh1 gh3 gh4 t20 gh0 t23 t22 t21 t24 gh5 gl0 gl1 gl2 gl3 gl4 gl5 serial peripheral interface the HI-8429 uses a spi (serial peripheral interface) for host access to the internal configuration, dac and data registers which program the sensor mode, threshold levels and store sensor status. host serial communication is enabled through the active low, chip select ( ) pin, and is accessed via a four- wire interface consisting of serial data input (si) from the host, serial data output (so) to the host, the serial clock (sck) and the . all read / write cycles are completely self-timed. the spi protocol specifies master and slave operation; the HI-8429 operates as a spi slave. the spi protocol defines two parameters, cpol (clock polarity) and cpha (clock phase). the possible cpol-cpha combinations define four possible spi modes. the HI-8429 operation is based on mode 0 (cpha = 0, cpol = 0), where input data for each device is clocked on the rising edge of sck, but data is also clocked out on the positive edge, see fig 14. as seen in spi timing diagrams figures 6-10, spi mode 0 holds sck in the low state when idle. the spi bus transfers serial data in multiples of 8, 9 or 24 bits, depending on the type of data and number of devices. once is asserted, the rising edge of sck shifts the input data into the slave devices, starting with each byte's most-significant bit. a rising edge on completes the serial transfer and re-initializes the HI-8429 spi for the next transfer. to improve immunity from noise on , a write will only occur after 8 scks are received. however if goes high after this and before a word transfer is complete, the incomplete byte will be latched into the device. both master and slave simultaneously send and receive serial data (full duplex), per figure 6. the HI-8429 maintains high impedance on the so output whenever is high. the maximum sck frequency is 10mhz. the HI-8429 logic is fully static and therefore there is no minimum sck speed. cs cs cs cs cs cs cs HI-8429 msb msb lsb lsb threshold register spi transfers to program the dac thresholds, the sel1 pin is held high and sel0 held low, see table 1. reading and writing to threshold registers uses the same sequence and requires transferring 24 bits (four sets of 6 bits) of continuous data, see figure 9. thresholds are set by adjusting the dac settings, according to table 2. as with the other registers, data can be daisy chained between multiple series spi coupled devices (see figure 12), an extra 24 clock cycles are required for each extra device. sensen config bit bit # table 2. sensor threshold table open or > ghi 1 (gnd/open) 24:19 < glo 1 (gnd/open) 18:13 open or < vlo 0 (supply/open) 12:7 > vhi 0 (supply/open) 6-1 sel0 sel1 spi function 0 read/write to configuration register (9bits) 1 x read/write to threshold register (24 bits) table 1. spi function table 0 0 1 read sensor data (8 bits)
holt integrated circuits 7 functional description (cont.) HI-8429 functional description (cont.) cr9 high z high z cs so si sck (spi mode 0) figure 6. nine-bit configuration register write example sel0 cr8 cr7 cr6 cr4 cr3 cr2 cr1 ncd9 new configuration register data (ncd9-1) is loaded into configuration register on rising edge cs cr5 ncd9 ncd8 ncd7 ncd6 ncd4 ncd3 ncd2 ncd1 ncd5 ncdn = new configuration register bits to be written to cr crn = old configuration register bits read from cr prior to cr write figure 7. 9bit configuration register write (p example added to make 2-bytes) cs si sck spi mode 0 12 3 4 5 67 high z 8 12 3 4 5 678 byte 2 sel0 so byte 1 x xxxxx x ncd 9 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 x high z xxxxxx cr1 ncd 8 ncd 7 ncd 6 ncd 5 ncd 4 ncd 3 ncd 2 ncd 1 ncd 9 new configuration register data (ncd9-1) is loaded into configuration register on rising edge cs ncdn = new configuration register bits to be written to cr crn = old configuration register bits read from cr prior to cr write x = dont care padding bits sel1 sel1 data register spi transfers according to the spi function table 1 the spi data path is selected by the control inputs sel1:0, . to read sensor data the sel0 pin should be high. when goes low, the output of each sensor is latched into the data register and dr8 is output at so. the next 7 rising edges of sck shift out data register bits 7 through 1. simultaneously, data presented at si is shifted into the data register, dr8 is written on the first rising edge of sck and dr1 on the eighth sck rising edge. cs the eighth sck edge also causes the new dr8 value to be output at so (see figure 8). this data transfer method allows multiple HI-8429 devices to be daisy-chained such that the data registers from each device are cascaded to form a single shift register. figure 12 shows a typical configuration of three daisy-chained HI-8429s to form a 24-input sensor array. note that when reading from more than one device, must remain low throughout the data read sequence. taking high and then low again between eight-bit reads will cause the sensor data to be re-latched into the data registers, overwriting data shifted in from earlier HI-8429s in the chain. see figure 10 for an example of a 24-bit data register read operation. cs cs
cs si sensen sck spi mode 0 12 3 4 5 67 high z 8 12 3 4 5 678 12 3 4 5 67 byte 2 byte 3 so byte 1 si16 si15 si14 si13 si12 si11 si10 si9 si8 si7 si6 si5 si4 si3 si1 si2 valid dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 si16 si14 si13 si12 si11 si10 si9 si8 si7 si6 si5 si4 si3 si1 si2 si15 high z si data is shifted out of so after 8 sck cycles sensor state is latched into data register on falling edge of cs 8 sel1 figure 10. 3-byte spi daisy-chain data register read example figure 9. 24-bit spi write and read threshold example cs si sck spi mode 0 12 3 4 5 67 high z 8 12 3 4 5 678 12 3 4 5 67 byte 2 byte 3 byte 1 t16 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t1 t2 high z 8 t24 t23 t22 t21 t20 ti9 t17 t18 sel0 sel1 s0 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p1 p2 p24 p23 p22 p21 p20 p19 p17 p18 tn = new threshold bit pn = old threshold bit p1 t24 si8 dr8 high z high z cs so si sck (spi mode 0) figure 8. single-byte data register read sel0 valid sensen dr7 dr6 dr5 dr4 dr3 dr2 dr1 si8 sel0 HI-8429 holt integrated circuits 8
functional description (cont.) 24 channel sensor application using HI-8429 host controller sck cs mosi HI-8429 device 2 HI-8429 device 3 si miso sck cs so so so HI-8429 device 1 sense8 so sense7 sense6 sense5 sense4 sense3 sense2 sense1 sense8 sense7 sense6 sense5 sense4 sense3 sense2 sense1 sense8 sense7 sense6 sense5 sense4 sense3 sense2 sense1 si si si sel1 sel0 sck cs sel1 sel0 sck cs sel1 sel0 sck cs sel1 sel0 figure 11. debounce data delay data[8:1] ddd t sense[8:1] valid functional description (cont.) holt integrated circuits 9 figure 12. multiple chip ?daisy-chain? connection 24 channel sensor application using HI-8429 host controller sck cs mosi HI-8429 device 2 HI-8429 device 3 si miso sck cs so so so HI-8429 device 1 sense8 so sense7 sense6 sense5 sense4 sense3 sense2 sense1 sense8 sense7 sense6 sense5 sense4 sense3 sense2 sense1 sense8 sense7 sense6 sense5 sense4 sense3 sense2 sense1 si si si sel1 sel0 sck cs sel1 sel0 sck cs sel1 sel0 sck cs sel1 sel0 int int t int function the output will produce an output whenever a sensor input changes. there will be a delay before the interrupt is produced and data updated, as shown in figure 11. this delay will depend upon the setting of dnbc, when dnbc is high the delay will be much longer due to the delay through the debounce circuitry. if the signal is used and mechanical contacts are also used for the sense circuit, it is recommended to enable debouce. int int HI-8429
holt integrated circuits 10 lightning protection all sensen inputs are protected to rtca/do-160g, section 22, categories a3 and b3, waveforms 3, 4, 5a, 5b with no external components. table 3 and figure 13 give values and waveforms. higher levels of lightning protection can be implemented using a series resistor and a tvs, see application note an-305 for recommendations. figure 13. lightning waveforms table 3. waveform peak amplitudes level waveforms 3/3 4/1 5a/5a voc (v) / isc (a) voc (v) / isc (a) voc (v) / isc (a) 3 600/24 300/60 300/300 5b/5b voc (v) / isc (a) 300/300 0.0 0.3 0.5 0.8 1.0 voltage waveform 4 t2 t1 v(%) t1 = 6.4s +/-20% t2 = 69s +/-20% t 50% peak 0.0 0.3 0.5 0.8 1.0 current/voltage waveform 5a t2 t1 i/v (%) t1 = 40s +/-20% t2 = 120s +/-20% t 50% peak -1.0 -0.5 0.0 0.5 1.0 t voltage/current waveform 3 peak 50% v/i (%) 1us/div. 0.0 0.3 0.5 0.8 1.0 current/voltage waveform 5b t2 t1 i/v (%) t1 = 50s +/-20% t2 = 500s +/-20% t 50% peak functional description (cont.) HI-8429
holt integrated circuits 11 setting sensor thresholds by programming dac codes HI-8429 example assume the voltage dd the s are oi10 i> v the curves in figure 15 for vdd = 15v. o , use the 15v minimum curve. t , t is 9. t o i use the imum curve to guarantee a maximum 10 . the ing value from the curve in this case is c these values , we get 0 respectively by writing - to the dac threshold register (see functional description section). , the values 0x 0x 0x1 0x are converted to the binary value supply is v = 15v and system threshold requirement : gnd/open sensors with gl < 4.5v and gh > .5v. supply/open sensors with vh 12 . for the gnd/open thresholds, use t guarantee a minimum 4.5v threshold a 4.5v he dac code reading 1 his is the gl dac setting . similarly for gh , 15v max correspond 47. onverting to hexadecimal x13 and 0x2f . similarly for the supply/open thresholds, the four dacs are programmed together one 24 bit word vl 6v .5v threshold use t guarantee a minimum v threshold a . v he dac code reading his is the l dac setting. similarly for h , 15v max v threshold correspond . onverting to hexadecimal x and 0x . for the above example 13 2f e 3a 010011 101111 011110 111010 and sent to the dac threshold register, msb first. o < and the curves in figure 17 for vdd = 15v. o 6.0 , use the 15v minimum curve. t 6 0 , t is 30. t v o v i use the imum curve to guarantee a maximum 12.0 . the ing value from the curve in this case is 58 c these values , we get 0 1e 3a respectively
holt integrated circuits 12 gnd/open sense thresholds versus dac code HI-8429 figure 15. gnd/open sense thresholds versus dac code for vdd = 15v figure 14. gnd/open sense thresholds versus dac code for vdd = 12v
holt integrated circuits 13 supply/open sense thresholds versus dac code HI-8429 figure 17. supply/open sense thresholds versus dac code for vdd = 15v figure 16. supply/open sense thresholds versus dac code for vdd = 12v
holt integrated circuits 14 note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. absolute maximum ratings recommended operating conditions supply voltage vlogic ................................. 3.13v to 3.47v vdd ................................. 11.4v to 15.75v digital inputs .......................... 0 to vlogic sense inputs ......................... -4.0v to 49v operating temperature range industrial screening ............. -40c to +85c hi-temp screening ............. -55c to +125c voltages referenced to ground digital supply voltage (vlogic) ......................... -0.3v to +5v analog supply voltage (vdd) .......................... -0.3v to +18v discrete input voltage range (dc) ................... -80v to +80v (ac, 60 - 400hz) ................... 115vrms continuous power dissipation (ta=+125c) ......... 1.7w solder temperature (reflow) ............................. 260c junction temperature ............................. 175c storage temperature ............................ -65c to -150c logic input voltage range ................ -0.3v to vlogic+0.3v HI-8429
holt integrated circuits 15 d.c. electrical characteristics v = 3.3v +/- 5%, v = 12.0v to 15v , gnd = 0v, t = operating temperature range (unless otherwise specified). logic dd a +/-5% +/-5% parameter sym condition min typ max unit logic inputs / outputs sense inputs, configured as ground / open (internal pull-up). power supply high level input voltage v v = 3.3v 2.0 v low level input voltage v v = 3.3v 0.8 v input hysteresis voltage, sck input v note 1. 50 mv high level output voltage v i = -20 a v -0.1 v i = -4 ma, v = 3.0v 2.4 v low level output voltage v i = 20 a 0.1 v i = 4 ma, vlogic = 3.0v 0.4 v input leakage current ( i v = v or ground -10 +10 a tri-state leakage current, so output i v = v or ground -10 +10 a high level sense pin to ground resistor r resistor from sense to ground to 50 k guaranteed high input condition high level input current i v = 28v, vdd = 15v 17 100 a v = 49v, vdd = 15v 45 250 ua low level sense pin to ground resistor r resistor from sense to ground to 500 guaranteed low input condition minimum hysteresis (vghi - vglo) hys 4 dac lsbs logic supply current i v = v or ground, 1.8 3.0 ma sense pins open analog supply current i v = v or ground sense pins open 15 24 ma sense pins = ground 23 33 ma note 1. guaranteed but not tested. ih logic il logic chys oh out logic out logic ol out out in in logic oz out logic ih ghi ghi ghi il go logic in logic dd in logic no pull-ups or pull-downs) input leakage current ( , dnbc, and sel1 pins, 10k pull-up / pull-downs) i v = v or ground 335 a low level input current i v = 0v, v = 15v -0.8 -1.0 -1.8 ma high level input current i v = 28v, v = 15v 0.6 0.8 1.35 ma low level input current i v = 1v, v = 15v 50 a minimum hysteresis (vshi - vslo) hys 4 dac lsbs mr inp in logic glo glo dd shi shi dd slo slo dd so sense inputs, configured as supply / open (internal pull-down). HI-8429
sck frequency f 50% duty cycle 0.1 10 mhz sck pulse width t 50 ns set-up time, sck to low t 30 ns hold time, max w su1 cs cs cs cs cs cs cs cs cs cs mr int low to sck t 25 ns set-up time, sense valid to low t 500 ns hold time, low to sense not valid t 15 s set-up time, si to sck rising t 25 ns hold time, sck rising to si not valid t 25 ns set-up time, sel valid to low t 30 ns hold time, high to sel not valid t 25 ns propagation delay, low to so valid t so loaded with 50pf to ground 105 ns propagation delay, sck rising to so valid t so loaded with 50pf to ground 90 ns propagation delay, rising to so hi-z t so loaded with 50pf to ground 80 ns recovery time t 20 ns logic input capacitance (sck, , si) c guaranteed but not tested 10 pf logic output capacitance (so hi-z) c guaranteed but not tested 15 pf pulse width t 1 s pulse width int 1 s data and interrupt delay (dnbc = low) t 4us data and interrupt delay (dnbc = high) ts 100 ms time between debounce samples t 25 ms h1 su2 h2 su3 h3 su4 h4 p1 p2 p3 csr in out mr sd d db ac electrical characteristics holt integrated circuits 16 v = 3.3v +/- 5%, v = , gnd = 0v, t = operating temperature range (unless otherwise specified). logic dd a 12.0v +/-5% to 15v +/-5% parameter sym condition min typ max unit HI-8429
holt integrated circuits 17 HI-8429 figure 18. switching waveforms si so hi impedance t p1 msb hi impedance cs sck sel1:0 su1 t h1 t su2 t csr t max 1/f sense valid su4 t valid valid h4 t w t h2 t su3 t h3 t h1 t t p2 t p3 alternative package configurations (40-pin qfn) -11 -12 -13 sense8 - 14 -15 -16 so-17 -18 -19 -20 int mr 40 - 39 - 38 - 37 - 36 - dnbc 35 - sel1 34 - vdd 33 - 32 - 31 - -1 sense1 - 2 sense2 - 3 sense3 - 4 sense4 - 5 sense5 - 6 sense6 - 7 sense7 - 8 -9 -10 30 - 29 - gnd 28 - 27 - vlogic 26 - 25 - sel0 24-si 23 - 22 - sck 21 - cs HI-8429pci HI-8429pct HI-8429pcm
holt integrated circuits 18 HI-8429 hi - 8429xx x x ordering information part number lead finish blank tin / lead (sn /pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40c to +85c i no t -55c to +125c t no m -55c to +125c m yes part number package description 8429ps 20 pin plastic thermally enhanced soic, wb (20hwe) 8429pc 40 pin plastic chip-scale, qfn (40pcs)
p/n rev date description of change ds8429 new 10/15/14 initial release. a 11/13/14 change vdd range to (12v +/-5% to 15v +/-5%. update dac curves. b 02/19/15 add 40-pin qfn package option. revision history holt integrated circuits 19 HI-8429
package dimensions holt integrated circuits 20 20-pin plastic small outline (esoic) - wb (wide body, thermally enhanced) millimeters (inches) package type: 20hwe bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) detail a 0 to 8 2.181 0.131 (0.086 0.005) bottom view top view 0.835 0.435 (0.033 0.017) 0.200 0.100 (0.008 0.004) 0.419 0.109 (0.016 0.004) 1.27 (0.50) bsc see detail a 0.215 0.115 (0.008 0.005) 10.33 (0.407) bsc 12.80 (0.504) bsc 7.50 (0.295) bsc 5.335 0.385 (0.210 0.015) 7.495 0.385 (0.295 0.015) electrically isolated heat sink pad on bottom of package connect to any ground or power plane for optimum thermal dissipation package type: 40pcs 6.00 .10 6.00 .10 4.1 .05 4.1 .05 0.40 .05 0.25 typ. 0.50 bsc 0.2 typ 0.90 .10 40-pin plastic chip-scale package (qfn) millimeters see detail a detail a 0.02 typ. 0.90 .10 electrically isolated pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)

▲Up To Search▲

Price & Availability of HI-8429

	To Download HI-8429 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .